An analog-to-digital converter (ADC) which converts an analog signal into a digital signal in order to perform various processes in a digital circuit or the like is widely used for an LSI (Large Scale Integration) or the like in a wire and/or wireless electronic device.
By the way, the ADC consumes much electric power and most of the electric power consumed in the LSI is consumed in the ADC. Accordingly, for example, in an electronic device such as a wireless portable terminal or the like, in order to realize a long-time battery operation, low power consumption is strongly required. For this reason, a technology for suppressing the electric power consumed in the ADC has been developed.
In Japanese Patent Application Laid-Open No. 2003-101411, a parallel type ADC which has a reference voltage generation circuit for outputting m reference voltages based on bit precision of a digital output signal, n comparators, and an encoder for encoding the outputs of n comparators and outputting a digital output signal is proposed. The number n of the comparators is set to a number smaller than the number m of the reference voltages and whereby a circuit scale is reduced. Therefore, the power consumption can be reduced.
In Japanese Patent Application Laid-Open No. 2004-214905, a variable resolution type ADC is proposed. The variable resolution type ADC outputs a digital output signal is obtained by synthesizing the digital signals outputted from conversion stages that are arranged at a subsequent stage of a sample hold circuit and connected in cascade. The sample hold circuit includes sample hold units, the number of which is determined according to the required resolution, and each sample hold unit is operated or stopped separately according to the resolution. As a result, the electric power consumed by the sample hold unit that is stopped can be reduced.
Japanese Patent Application Laid-Open No. 2008-177639 discloses a technology that a first resolution applied when a first signal for synchronization establishment is converted into a digital signal and a second resolution applied when a second signal including reception information is converted into the digital signal are switched. Additionally, an ADC in which the power consumption when performing the conversion into the digital signal at the second resolution is greater than the power consumption when performing the conversion into the digital signal at the first resolution is provided. Until the synchronization is established based on the first signal, the conversion into the digital signal is performed at the first resolution. As a result, the power consumption can be suppressed until the synchronization is established.
In Japanese Patent Application Laid-Open No. 2010-166447, a pipeline type ADC in which a plurality of residual calculation stages that are connected in cascade are provided and the resolution of the residual calculation stages other than the last stage can be changed is proposed. Control is performed so that the resolution in each residual calculation stage is increased when a high S/N (Signal/Noise) ratio is required and the resolution is lowered when the electric power is reduced at the sacrifice of the S/N ratio. As a result, a time average electric power can be reduced.
However, the inventions described in the above-mentioned patent documents have the following problems. Namely, in the parallel type ADC disclosed in Japanese Patent Application Laid-Open No. 2003-101411, because the number n of the comparators is set to a number smaller than the number m of the reference voltages, it is difficult to convert a full scale analog signal into a digital signal at high resolution. Therefore, a problem in which while performing the conversion into the digital signal at a resolution according to a signal characteristic of the analog signal that is a conversion object, the power consumption cannot be reduced occurs.
In the variable resolution type ADC disclosed in Japanese Patent Application Laid-Open No. 2004-214905, variable resolution is used and each of the plurality of sample hold units used in the sample hold circuit is separately operated or stopped according to the resolution. However, a configuration in which each conversion stage connected to the sample hold circuit always operates is used. Therefore, a problem in which the power consumption cannot be sufficiently suppressed occurs.
In the invention disclosed in Japanese Patent Application Laid-Open No. 2008-177639, until the synchronization is established based on the first signal with the S/N ratio greater than the S/N ratio of the second signal, the first signal is converted into the digital signal at the first resolution smaller than the second resolution and whereby, the power consumption can be reduced until the synchronization is established. However, a problem in which the power consumption cannot be reduced after the synchronization has been established occurs.
In the invention of Japanese Patent Application Laid-Open No. 2010-166447, in order to reduce the power consumption, a control in which the resolution in each residual calculation stage is increased when a high S/N ratio is required and the resolution is lowered when the power consumption is reduced at the sacrifice of the S/N ratio is performed. However, this control has a problem in which all the residual calculation stages operate independently of the resolution and the power consumption cannot be sufficiently reduced.